Associate Professor Donald Bailey, Institute of Information Sciences and Technology, Massey University, Palmerston North, New Zealand
FPGAs are increasingly being used as an implementation platform for real-time image processing applications because their structure is able to exploit spatial and temporal parallelism. However, mapping an image processing algorithm onto hardware is not a trivial task as many of the development tools are relatively low level. There are typically four stages involved in designing an FPGA based image processing system: problem specification; algorithm development; architecture selection; system implementation. For each stage, the key challenges are identified, and the differences between developing a software and hardware based solutions are highlighted. Timing, resource and bandwidth constraints often necessitate a significant change to the form of the algorithm and hence the implementation. A range of architectural solutions to some of these problems are illustrated through the mapping of some common image processing operations. The development process is made more difficult as the large volume of data from real-time images makes debugging difficult. A spectrum of system configurations are described, from a hosted system where the FPGA is a co-processor or accelerator for a more conventional software based system, through to a stand-alone configuration where all of the processing is implemented on the FPGA.The tutorial will conclude with some case studies of algorithms we have implemented on FPGAs.
A basic understanding of image processing is assumed. The tutorial is targeted at those who want an introduction to the advantages, and also some of the problems of mapping image processing algorithms to hardware, and in particular onto FPGAs. The examples will focus mainly on low-level image processing operations and preprocessing.
Associate Professor Donald Bailey gained his BE(Hons) and PhD degrees in Electrical and Electronic Engineering from University of Canterbury, New Zealand in 1982 and 1985. After spending 2 years applying image analysis techniques to the wool and paper industries within New Zealand, he spent 2 1/2 years as a visiting researcher at the ECE Department at the University of California at Santa Barbara. In 1989, he returned to New Zealand as Director of the Image Analysis Unit at Massey University. In 1998 he moved to the Institute of Information Sciences and Technology where he is currently a leader of the Image and Signal Processing Research Group. He is subject advisor for the Electronics and Computer Systems Engineering BE major. His primary research interests are in the application of signal processing, image analysis and image processing techniques.